Hardware Security Lattice Paper Accepted to ACM TODAES

latticeOur work on formalizing gate level information flow tracking (GLIFT) to handle multiple labels was accepted to the ACM Transactions on Design Automation of Electronic Systems (TODAES). The article titled “Gate Level Information Flow Tracking for Security Lattices” extends the ability to track only two labels (e.g., trusted/untrusted) to larger number of comparable labels. For example, we could mark hardware cores as “verified built in-house”, “tested built in-house”, “verified external source”, “tested external source”, and “untested external”. In each case, there is a varying level of trust. With the ability to track these multiple labels, we can then understand how the various hardware cores affect each other. The lead author was our new post-doc Vinnie Wei Hu with co-authors Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner.

Embedded System Design Class Projects

CSE 145 and CSE 237Des2 combine the talents of undergraduate and graduate students to develop quarter long projects on a variety of topics in embedded systems. This year saw the development of a number of great projects. Many were proposed by Ryan and members of our research group. A number of them came directly from the students. All of the students put in countless hours to develop these projects, which were highlighted in news releases from the Jacobs School of Engineering and a two part series at Calit2 (Part 1, Part 2). The classes will be offered again in Spring 2015. Start thinking of some good ideas for next year!

Hardware Security Technology Highlighted in Various News Outlets

aes_flowsThe hardware security techniques developed in our research group, and being commercialized by Tortuga Logic, recently received a significant amount of news coverage. This all started with a story from the Jacobs School of Engineering that got picked up by a number of different venues including ACM TechNews, Calit2, R&D Magazine, Science Codex, Counsel and Heal, Phys.org, Science Daily, RF Globalnet, Product Design and Development, Red Orbit, and probably several others that I have missed. The International Business Times also interviewed Ryan and put out a rather lengthy story.

Three papers accepted to FPL 2014

fpl-mapOur group continues its success at FPL following up last years three papers and best paper award with three papers in this upcoming FPL to be held in Munich, Germany in September. Pingfan was the lead author on the paper “Hardware Accelerated Novel Optical De Novo Assembly for Large-Scale Genomes” which develops a hardware accelerated solution for genome matching. This paper was done in collaboration with our friends at BioNano Genomics. The second accepted paper was “Improving FPGA Accelerated Tracking with Multiple Online Trained Classifiers” with Matt as the lead author. This paper utilizes the performance of FPGAs to create a robust tracker by training the features in an online manner. Dajung was the lead author on the final paper, “High Throughput Channel Tracking for JTRS Wireless Channel Emulation”, which developed a channel tracker which is an integral part of the wireless channel emulator project with Toyon Research Group. Congrats and beifall to all the authors!

Two more add “Dr” to their names

IMG_2091IMG_2101Matt and Jason successfully defended their theses bringing the total to three people who have graduated with PhDs from the Kastner Group this year. Matt’s research focused on developing a Smart Frame Grabber framework to ease the development of building computer vision applications using heterogeneous systems. Jason’s research on hardware security developed the first method for determining the existence of timing channels in hardware.

Both will be missed, but will not be going too far. Matt will work at Google in Irvine though will still reside in the San Diego area. Jason will be full-time CEO at Tortuga Logic. Congrats to both!

First Technique for Detecting Hardware Timing Channels

test_flowThe article “Leveraging Gate Level Properties to Identify Hardware Timing Channels” was accepted to the IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD). Jason was the lead author along with co-authors Sarah Meiklejohn (UCSD), Timothy Sherwood (UCSB), and Ryan. This paper formalizes how Gate Level Information Flow Tracking can be used to detect timing channels: a form of information leak where secret information can affect run time.

Dr. Chris Barngrover Defends His PhD Thesis

IMG_1024Congratulations to Dr. Barngrover on successfully defending his thesis titled “Automated Detection of Mine-Like Objects in Side Scan Sonar Imagery”. His PhD research focused detecting underwater mines using side scan sonar on autonomous underwater vehicles. He developed a number of computer vision techniques that can accurate detect these mines. Additionally, he developed the first method of using a brain-computer interface system to quickly identify the mines. During his time in the Kastner Group, he also became a skilled fisherman as evidenced by the nice rainbow trout that he caught during one of our group retreats in Mammoth. Dr. Barngrover will continue to work at SPAWAR after graduation.

Team FANGS Wins Honorable Mention at Cornell Cup

cornell cupTeam FANGS took home an honorable mention at the Cornell Cup. The team consisted of Engineers for Exploration members Xavier Tejeda, Dominique Meyer, Andrew Elgar, Kevin Cheng, and Jorge Pacheco. The team was advised by Ryan. These undergraduate students spent the past several months developing a terrestrial vehicle that is capable of remotely monitoring wolves at the California Wolf Center. They competed with over 30 teams in Orlando, FL on May 2-3.