National Science Foundation Secure and Trustworthy Computing Award

hardware-securityWe recently received an NSF grant on “Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs”. The project will develop quantitative hardware security metrics that enable designers to precisely evaluate the security of the system. We do this by employing statistical measures on the amount of uncertainty and information flow that is present across different portions of the hardware. These metrics are oblivious to the types of variables under consideration. Thus, we can assess both functional security properties related to confidentiality and integrity as well as covert channels. Our metrics enable the characterization of portions of the system that are potentially vulnerable to attacks. And they determine the effectiveness of mitigation techniques on the overall security of the system. The end result is more secure hardware, which leads to safer and more secure computing devices.

Link: grant information

RIFFA 2.2 Released

riffaThe latest and greatest version of RIFFA has been released. RIFFA is a framework that enables designers to easily communicate between FPGAs and CPUs over a PCIe bus. This work was born out of immense frustration of building complete hardware accelerated systems. Previous to RIFFA, there was no easy to use way to create an CPU/FPGA hybrid system that could take advantage of the power computing abilities of FPGAs while at the same time utilize the flexibility and interoperability of software running on CPUs. RIFFA changed that and is currently being used by designers around the world.

The latest updates to RIFFA include a complete redesign of the FPGA interfacing. This enables user to easily extend it to work with other FPGAs and development boards. The primary developers of this project are Kastner Group PhD alumni Matt Jacobsen and current PhD student Dustin Richmond. The work has been funded by Altera, Intel, and Xilinx. It was the recipient of the FPL Community Award in 2013.

RIFFA webpage
Xilinx Xcell Daily Blog
UCSD Qualcomm Institute Press Article
UCSD Computer Science and Engineering Press Article
FPL Community Award

NCWIT Undergraduate Research Award

antonella_stereo_cameraThe NCWIT Collegiate Award Honorable Mention – given by the National Center for Women & Information Technology and HP – was presented to Antonella Wilby. Antonella has been a member of our Engineers for Exploration program working on a project related to developing underwater sensing technology to document the shipwrecks and other underwater archaeological artifacts. Each honorable mention received a $500 cash gift, an HP backpack and gift, and recognition at an awards ceremony at the NCWIT 2015 Summit in Hilton Head, SC. Congrats to Antonella!

NCWIT Announcement

New Metrics for Hardware Security

stopwatchSide channels are a commonly exploited to derive secret information from hardware. These leak information through unintended sources, e.g., the amount of time to perform an encryption. They have been shown to be a powerful attack to extract cryptographic keys and other confidential information. There are many defenses against these timing side channel attacks. Most of them perform some sort of randomization in an attempt to mask the computation time. Yet, it has been difficult to quantify the benefit of these defenses.

Our recent research provides a metric to allow designers to determine how resilient their design is in the face of a side channel attack. While there are many metrics for hardware designers, these have focused on performance, power, and area. We developed information theoretic approaches and showed that they can be used to quantify timing-based information leakage. This is detailed in our recently accepted paper, “Quantifying Timing-Based Information Flow in Cryptographic Hardware” at the International Conference on Computer Aided Design. Vinnie will present the paper in Austin, TX in November. Congrats to all the authors: Baolei Mao, Vinnie Wei Hu, Alric Althoff, Janarbek Matai, Jason Oberg, Dejun Mu, Tim Sherwood, and Ryan Kastner.

NPU Visiting Professor

IMG_3616Ryan and Vinnie travel to Northwestern Polytechnical University (NPU) in Xi’an China to continue our collaboration with Dr. Dejun Mu and his students. Ryan was given a visiting professor position as part of the NPU Special Zone for Talents. Vinnie was a gracious host, showing Ryan all of the sites in Xi’an and making sure he was well feed. The picture is of the Famen Temple outside of Xi’an, and of course, Ryan’s foot (to add to his foot picture collection).

Embedded Systems Design Projects

blueraveThe end of the academic year brought to close yet another successful set of projects in Ryan’s CSE 145 – Embedded Systems Design Project class. The focus of the class is to let the students understand the end to end process of building an embedded system. Along the way, they also learn how to better present their project ideas, write technical documents, create promotional videos, and even how to create startups from their ideas.

There were 14 projects this year. They ranged from playful (e.g., an system that automates the process of making a light show for raves — this BlueRave team is in the picture) to much more serious (e.g., a device to detect when a person is having an epileptic seizure). And there were many other projects in between. You can see all of the final videos on the class project website. Or you can learn about a few of the other projects in the news release from Calit2.

A special thanks to Tiffany Fox for teaching the students how to give outstanding presentations, and providing the students with critiques on their oral presentations. And the class very much enjoyed special guest lectures from Jay Kunin (entrepreneurship), and Mike Kalichman (ethics).

First Nonnegative Least Squares Architecture Developed for FPGAs

NNLS_ARCH_FPL15Nonnegative least squares (NNLS) is important in many application domains including graphics, imaging, digital signal processing, and compressive sensing. Our paper titled “A Scalable FPGA Architecture for Nonnegative Least Squares Problems” details the first FPGA architecture for this application; it will be published in the International Conference on Field-programmable Logic and Applications (FPL). The paper describes two different architectures that provide a low cost, low power, and high performance computing solution. It is the first NNLS implementation for an FPGA. Alric Althoff is the lead author along with Ryan. FPL is a premier conference in the area of reconfigurable computing and FPGAs. It is held in London, England this coming September.

Sweeping the Inaugural CSE Research Awards

Computer Science and Engineering - UC San Diego - End of Year Awards 2015The UCSD Department of Computer Science and Engineering had its first annual award ceremony to highlight outstanding contributions to research, teaching, and diversity at both the graduate and undergraduate levels. Our group won the best research awards at both the undergraduate and graduate level. Pingfan Meng received the graduate research award to cap off an outstanding year in which he won the best paper award at FPL, and continued his stellar research on heterogeneous computing. Antonella Wilby received the undergraduate award; she has also had an eventful year having received a National Geographic Young Explorer Award earlier this academic year. Her work develops technologies for documenting the Vaquita – the worlds most endangered marine mammal.

CSE Story
Awards Ceremony Video
Posted in Uncategorized

FDA Warns about Security Vulnerabilities

infusion pumpThe Food and Drug Administration recently issued a warning about security vulnerabilities in infusion pumps. Unfortunately, this is likely just the start of such warnings. Clearly the medical device manufacturers need to consider security as a first order design constraint. Ryan and other embedded security experts discusses these issues in a recent article on Healthcare Info Security.

Faster Mine Detection Using Computer Vision and EEG

mine_detectionUnderwater mines remain a concern for ships around the world. Mines still remain from World War II throughout the Mediterranean Sea, and in the Persian Gulf from Desert Storm and other recent military activities in that region. We developed techniques that combine computer vision with electroencephalogram (EEG) devices to enable the detection of mines in a much better and faster manner.

The current state of the art in mine detection has people scanning through large sonar images looking for the mines. This is a lot like “Where’s Waldo?”. Many objects look similar to mines, e.g., ripples in the sand. And it is even harder in some ways since the images are blurry and there is noise. Think about looking for Waldo with scratched and blurry glasses. We use computer vision algorithms to first detect potential locations of the mines, but they are not always accurate. These algorithms look for simple patterns, akin to looking for red and white stripes to find Waldo. But they can be tricked if similar patterns occur but they are not mines — just like the illustrators of “Where’s Waldo?” draw other objects with red and white stripes to fool the viewer. Thus, we give all of these potential mine locations from the computer vision algorithm to a human who can then verify if they are indeed mines or some object that looks like a mine. And since we prescreen these images, we can present them in a much faster manner to the human; we did it at 5 images per second by using EEG techniques.

This work was recently published in the Journal of Oceanographic Engineering, and was highlighted in the popular press (see links below). The authors are Chris, Alric, Paul DeGuzmann from Neuromatters, and Ryan.

Union-Tribune San Diego
ACM TechNews
UCSD Jacobs School of Engineering News
Product Design and Development
Scientific Computing
ECN Magazine
R & D Magazine