We had a busy, but enjoyable time at the International Symposium on FPGAs. It is always great to visit the beautiful Monterey Peninsula.
The festivities started on Sunday, when Dustin Richmond, Ryan Kastner, Jeff Goeders, and Mirjana Stojilović organized the Third Workshop on Security for Custom Computing Machines (SCCM) on Sunday. This hybrid event had 30+ people in person and another 30+ online. The presentations have all been posted on the SCCM website, which also has videos from last year. As part of this, Colin Drewes gave the first public presentation of our Pentimenti project, which describes a novel temporal analog side channel in FPGAs.
On Monday, Colin presented his UCSD MS research developing a time-to-digital converter (TDC) for FPGA security applications. TDCs are common sensors for measuring the on-chip voltage and inferring behaviors of other system tenants. Our Tunable Dual-Polarity TDC (repo, paper) can hone in on important times in the computation, e.g., around clock transitions, and extract more information about co-tenant computations. The project was one of the three best paper nominations. Unfortunately, we did not get the best paper, but we are honored to be in the top three. The research was a strong, multi-university collaboration between UC Santa Cruz, UC San Diego, and Georgia Tech Research Institute. Congrats to all the authors!
On Tuesday, Olivia Weng presented her research on co-design optimizations for implementing neural networks on FPGAs. This research is part of the Tailor project, which performs network architecture modifications that remove or shorten skip connections to optimize on-chip memory architectures.