The Kastner Research Group is getting ready for a European Vacation this coming March. We have three long papers accepted at Design Automation and Test in Europe (DATE) which will be held March 14-18, 2016 in Dresden, Germany. DATE is the premier European conference for electronic system design and test. The three papers are “Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs“, “Composable, Parameterizable Templates for High Level Synthesis“, and “Quantifying Hardware Security Using Joint Information Flow Analysis“. The first paper, authored by Pingfan Meng, Alric Althoff, Quentin Gautier, and Ryan Kastner, builds a machine learning framework to determine Pareto optimal designs from OpenCL to FPGAs, with a limited number of synthesis runs (which costs hours or days). The second paper, authored by Janarbek Matai, Dajung Lee, Alric Althoff, and Ryan Kastner, develops a framework for composing high-level synthesis applications from templates. The final paper was invited for a special session on system security. It focuses on a creating a novel hardware security design flow using quantitative metrics. It was authored by Ryan Kastner, Wei Hu, and Alric Althoff. Congrats to all of the authors!

A tradition unlike any other — the Kastner Research Group retreat. Most of the members of the group headed for a few days of adventure, research presentations, and high elevation mountain air last week. The fourth annual installment included the group hike up and around the Crystal Crag near Mammoth Lakes. The five mile hike, with over 1000 feet of elevation gain, was enjoyed by some more than others. But everyone made it and has some stories to tell. The picture shows the group (at least those that survived) with the Crystal Crag in the background. Next year we will try something a little less difficult, e.g., hiking up Mount Everest.

We are pleased to welcome Jeremy Blackstone as the newest PhD student in the Kastner Research Group. However, Jeremy is no stranger; he has worked with us for two summers. In Summer 2013, he worked as a member of the Engineers for Exploration program. Last summer he did research on the RIFFA project. Jeremy graduated magna cum laude in computer science from Howard University, where he also earned his M.S. degree

Jeremy Blackstone is the first graduate student selected to receive a fellowship from the Alfred P. Sloan Foundation Minority Ph.D. Program to do a doctorate in Computer Science and Engineering at the University of California, San Diego. He was also awarded a UC-HBCU fellowship. He graduated magna cum laude in computer science from Howard University, where he also earned his M.S. degree.

We recently received an NSF grant on “Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs”. The project will develop quantitative hardware security metrics that enable designers to precisely evaluate the security of the system. We do this by employing statistical measures on the amount of uncertainty and information flow that is present across different portions of the hardware. These metrics are oblivious to the types of variables under consideration. Thus, we can assess both functional security properties related to confidentiality and integrity as well as covert channels. Our metrics enable the characterization of portions of the system that are potentially vulnerable to attacks. And they determine the effectiveness of mitigation techniques on the overall security of the system. The end result is more secure hardware, which leads to safer and more secure computing devices.

Link: Research.gov grant information

The latest and greatest version of RIFFA has been released. RIFFA is a framework that enables designers to easily communicate between FPGAs and CPUs over a PCIe bus. This work was born out of immense frustration of building complete hardware accelerated systems. Previous to RIFFA, there was no easy to use way to create an CPU/FPGA hybrid system that could take advantage of the power computing abilities of FPGAs while at the same time utilize the flexibility and interoperability of software running on CPUs. RIFFA changed that and is currently being used by designers around the world.

The latest updates to RIFFA include a complete redesign of the FPGA interfacing. This enables user to easily extend it to work with other FPGAs and development boards. The primary developers of this project are Kastner Group PhD alumni Matt Jacobsen and current PhD student Dustin Richmond. The work has been funded by Altera, Intel, and Xilinx. It was the recipient of the FPL Community Award in 2013.

Links:
RIFFA webpage
Xilinx Xcell Daily Blog
UCSD Qualcomm Institute Press Article
UCSD Computer Science and Engineering Press Article
FPL Community Award

The NCWIT Collegiate Award Honorable Mention – given by the National Center for Women & Information Technology and HP – was presented to Antonella Wilby. Antonella has been a member of our Engineers for Exploration program working on a project related to developing underwater sensing technology to document the shipwrecks and other underwater archaeological artifacts. Each honorable mention received a $500 cash gift, an HP backpack and gift, and recognition at an awards ceremony at the NCWIT 2015 Summit in Hilton Head, SC. Congrats to Antonella!

NCWIT Announcement

Side channels are a commonly exploited to derive secret information from hardware. These leak information through unintended sources, e.g., the amount of time to perform an encryption. They have been shown to be a powerful attack to extract cryptographic keys and other confidential information. There are many defenses against these timing side channel attacks. Most of them perform some sort of randomization in an attempt to mask the computation time. Yet, it has been difficult to quantify the benefit of these defenses.

Our recent research provides a metric to allow designers to determine how resilient their design is in the face of a side channel attack. While there are many metrics for hardware designers, these have focused on performance, power, and area. We developed information theoretic approaches and showed that they can be used to quantify timing-based information leakage. This is detailed in our recently accepted paper, “Quantifying Timing-Based Information Flow in Cryptographic Hardware” at the International Conference on Computer Aided Design. Vinnie will present the paper in Austin, TX in November. Congrats to all the authors: Baolei Mao, Vinnie Wei Hu, Alric Althoff, Janarbek Matai, Jason Oberg, Dejun Mu, Tim Sherwood, and Ryan Kastner.

Ryan and Vinnie travel to Northwestern Polytechnical University (NPU) in Xi’an China to continue our collaboration with Dr. Dejun Mu and his students. Ryan was given a visiting professor position as part of the NPU Special Zone for Talents. Vinnie was a gracious host, showing Ryan all of the sites in Xi’an and making sure he was well feed. The picture is of the Famen Temple outside of Xi’an, and of course, Ryan’s foot (to add to his foot picture collection).

The end of the academic year brought to close yet another successful set of projects in Ryan’s CSE 145 – Embedded Systems Design Project class. The focus of the class is to let the students understand the end to end process of building an embedded system. Along the way, they also learn how to better present their project ideas, write technical documents, create promotional videos, and even how to create startups from their ideas.

There were 14 projects this year. They ranged from playful (e.g., an system that automates the process of making a light show for raves — this BlueRave team is in the picture) to much more serious (e.g., a device to detect when a person is having an epileptic seizure). And there were many other projects in between. You can see all of the final videos on the class project website. Or you can learn about a few of the other projects in the news release from Calit2.

A special thanks to Tiffany Fox for teaching the students how to give outstanding presentations, and providing the students with critiques on their oral presentations. And the class very much enjoyed special guest lectures from Jay Kunin (entrepreneurship), and Mike Kalichman (ethics).

Nonnegative least squares (NNLS) is important in many application domains including graphics, imaging, digital signal processing, and compressive sensing. Our paper titled “A Scalable FPGA Architecture for Nonnegative Least Squares Problems” details the first FPGA architecture for this application; it will be published in the International Conference on Field-programmable Logic and Applications (FPL). The paper describes two different architectures that provide a low cost, low power, and high performance computing solution. It is the first NNLS implementation for an FPGA. Alric Althoff is the lead author along with Ryan. FPL is a premier conference in the area of reconfigurable computing and FPGAs. It is held in London, England this coming September.