Three Papers Accepted at DATE

 The Kastner Research Group is getting ready for a European Vacation this coming March. We have three long papers accepted at Design Automation and Test in Europe (DATE) which will be held March 14-18, 2016 in Dresden, Germany. DATE is the premier European conference for electronic system design and test. The three papers are “Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs“, “Composable, Parameterizable Templates for High Level Synthesis“, and “Quantifying Hardware Security Using Joint Information Flow Analysis“. The first paper, authored by Pingfan Meng, Alric Althoff, Quentin Gautier, and Ryan Kastner, builds a machine learning framework to determine Pareto optimal designs from OpenCL to FPGAs, with a limited number of synthesis runs (which costs hours or days). The second paper, authored by Janarbek Matai, Dajung Lee, Alric Althoff, and Ryan Kastner, develops a framework for composing high-level synthesis applications from templates. The final paper was invited for a special session on system security. It focuses on a creating a novel hardware security design flow using quantitative metrics. It was authored by Ryan Kastner, Wei Hu, and Alric Althoff. Congrats to all of the authors!