As part of this year’s Design Automation Conference, I participated on the panel “Architecture, IP, or CAD: What’s Your Pick for SoC Security?”. That’s a bunch of acronyms and buzzwords related to the question of how to build more secure computer chips. DAC is one of the oldest, largest and most prestigious conferences in electronics design. It was also the first big research conference that I attended; I went to DAC in New Orleans in 1999 as an undergraduate (which was an eye opening experience in many regards), so I guess this was my 20th DAC anniversary.

I’ve been doing research in the hardware security space for a while now (more than 15 years!). I’ve seen this community grow from a niche academic community into a major focus at DAC (there were security sessions almost non-stop this year). And it was nice to see more hardware security companies on the floor including the amazing Tortuga Logic (full disclosure: I am a co-founder). Security clearly has become a major research and market push for the semiconductor and EDA industries.

I was the “academic” on this panel with two folks from industry — Eric Peeters from Texas Instruments and Yervant Zorian from Synopsys. Serge Leef from DARPA was the other panelist. Serge just went to DARPA from Mentor Graphics and is looking to spend a lot of our taxpayers money on hardware security. A very wise investment in my totally impartial opinion. I’m guessing that most of the audience was there to hear what Serge had to say and to see if any money fell out of his pockets as he left the room.

The panel started with short (5 min) presentations from each panelist and then there was a lot of time for Q&A from the moderator (the great Swarup Bhunia) and the audience.

My presentation talking points focused on how academics, industry, and government should interact in this space. My answer: industry and government should give lots of funding for academic research (again, I’m totally not biased here…). I also argued that there really isn’t all that much interesting research left in hardware IP security, which I defined as Trojans, PUFs, obfuscation, and locking. Finally, I gave some research areas that are more interesting for research including formalizing threat models and figuring out how to debug hardware security vulnerabilities. Both are no small tasks, and my research group is making strides in both.

During the open discussion there were many other interesting points related to industry’s main interests (root of trust, not Trojans, …), the number of hardware vulnerabilities there are in the wild, metrics, hardware security lifecycle, and so on.

It was a quick visit Vegas (~1 day), but you brought back some good memories, gave me some great food, and didn’t take too much of my money. All and all, a successful trip.

-Ryan

The SmartFin is a surfboard surfin embedded with a number of sensors that allow it to be opportunistically used to gather oceanographic data. The idea is to “crowdsource” the data from surfers all over the globe. This allows us to create fine-grained spatial and temporal sampling strategies to provide data that will ultimately help us better understand complex near-shore environment.

UCSD CSE undergraduate and Engineers for Exploration leader Jasmine Simmons is leading a team in our Engineers for Exploration program working to make the SmartFin even smarter. She has been working closely with oceanographer Phil Bresnahan to create the next version of the SmartFin. One of the major goals is to add the ability to use the SmartFin as a wave sensor. The goal to extract information about the ocean waves (frequency, amplitude, …) from the data gathered from the SmartFin inertial measurement unit (IMU). This is a challenging problem since the IMU data is noisy and the surfer may not always be in a position to collect good data about ocean waves. They are working on developing digital signal processing algorithms to extract the wave data from the sensors on the SmartFin.

The Science Mathematics and Research for Transformation (SMART) program is a US Department of Defense (DoD) scholarship aimed at training top talent in science, technology, engineering and mathematics. SMART fellows are paired with a DoD institution where they spend the summers working on research and then transition into those labs after graduation.

As part of the scholarship, Peter will continue his research with the Naval Information Warfare Center (NIWC) Pacific. Peter’s research looks at how to better use autonomous vehicles (drones and underwater vehicles) to create large scale 3D models. He was been doing research with NIWC Pacific — a large San Diego Navy research facility — for the past couple of years. SMART will allow him to continue this collaboration both during his PhD and after.

Peter is not the first SMART student in our lab. Dr. Chris Barngrover was given a SMART scholarship to fund his PhD thesis on developing novel technologies for finding mines in sonar images. Chris also worked with NIWC Pacific (then SPAWAR).

Higher-Order Functions are a common and convenient way to encapsulate design patterns in software development. However, they are not readily available in hardware design tools. This is because they rely on memory allocators to implement dynamic lists, polymorphism, and looping. These concepts are not very amenable to hardware synthesis.

Dustin presented a solution to this problem in the paper “Higher-Order Functions for C++ Synthesis” at CODES+ISSS as part of Embedded Systems Week. The project develops a library of higher-order functions for C++ High-Level Synthesis tools. We open-sourced these libraries and we hope that you use them. Check that out on github: github.com/drichmond/hops (hops stands for Higher-Order PatternS and also an ode to one of our favorite beverages.). ESWeek was in Torino, Italy so Dustin also found some free time to visit Mont Blanc (pictured).

Once again we had a good showing at 28th International Conference on Field Programmable Logic and Applications (FPL 2018). FPL is the premier European venue for publishing research results in the field of FPGAs and reconfigurable systems. This year, the conference was held in Dublin Ireland. Michael Barrow made the trip to present our two papers.

The first paper was “Everyone’s a Critic: A Tool for Exploring RISC-V Projects”, which describes a tool that provides a way to compare and evaluate the different RISC V architectures with a streamlined suite of tutorials, drivers, and deployment packages on the Pynq development board. The tool is open source at on the github repo: https://github.com/drichmond/RISC-V-On-PYNQ . This project was lead by Dr. Dustin Richmond with contributions by Michael Barrow.

The second paper was “A FPGA Accelerator for Real-Time 3D Non-Rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation”. This project developed a novel reconfigurable system that performs real-time 3D registration — a fundamental computer vision problem with applications in augmented reality, 3D modeling, and computer vision. The architecture was developed with Stephen Burns from Intel (and the result of the time project lead Michael Barrow internship there). Our system is more energy efficient and higher performing than comparable software or hardware approaches with a minimal reduction in registration accuracy.

Hardware design is not easy. It typically involves writing code in low-level languages like Verilog where you must specify how every operation works at every cycle. Modern processors perform billions of operations per second making this is a very difficult task! Yet, hardware design has become increasingly important and more pervasive with the advent of custom accelerators which are used in phones, cars, and in the cloud. We need more hardware designers, but unfortunately, hardware design is hard.

Dr. Dustin Richmond recently defended his PhD thesis that tackled this problem — increasing the accessibility of hardware development to non-hardware engineers through the use of common parallel patterns. As part of this, Dustin developed RIFFA (abstracting communication patterns) [1] and created a framework for synthesizing higher-order functions to hardware (abstracting computational patterns) [2].

As with most PhD students in our research group, Dustin had many side projects to distract him during his PhD career. Dustin played a key role in developing our 3D imaging system for creating 3D scans of Maya archaeological sites. This involved expeditions to Guatemala to scan ancient Maya structures, a run-in with a large black snake, and a publication in “Advances in Archaeological Practice” [3]. Dustin also built the hardware for a high framerate 3D imager in one of our first projects with Cognex [4]. This ultimately helped inform Cognex on how to build this sensor which is now a product. Dustin spent two separate internships at Altera (now Intel) and Xilinx. I’m not entirely sure how he fit all of that into one PhD, but certainly, it is impressive.

While PhD defense is mostly focused on research, it should be noted that Dustin has an equally impressive record with university service and teaching. His efforts to our community have been documented in other posts (CSE award and UCSD Graduate Student Association Awards). As a TA, he took on a major revision of our hardware curriculum in the Wireless Embedded Systems Masters Program. He introduced the Xilinx Pynq platform with a series of labs, lectures, and assignments. For the final project, he organized a hackathon where each group was able to make an impressive project in less than two weeks. We will continue to use this curriculum moving forward in that and other classes.

Dustin will continue on the academic route moving back to the Pacific Northwest to be a postdoctoral scholar with Michael Taylor and Luis Ceze. Look for him on the academic job market in 1-2 years.

-Ryan

Dustin Richmond (center with redish shirt) along with the other PhD award winners.

The Department of Computer Science and Engineering gave Dustin Richmond one of its annual awards for “Excellence in Service/Leadership”. Dustin has been a key leader in departmental activities since the day that he arrived N years ago. He has been an active community leader in our department, interacting with staff, students, and faculty to improve our community by organizing and motivating others to do the same. For example, he was the student chair of the department Graduate Community Council. As part of this, he proposed, designed, and oversaw the remodel of Chez Bob. These changes have transformed the lounge into a common meeting area. For several years he also managed the Graduate Student Association budget, allocating money to ideas and projects that improve the quality of life, evaluating and funding ideas that clearly benefit a broad swath of the department, and helping students make their ideas a reality. Dustin also organized an NSF Graduate Research Fellowship Panel, where current applicants can ask questions, and receive feedback about their essay writing service. He has mentored and encouraged other students in the community and recruited faculty with past NSF application experience to participate. This provides a valuable benefit to incoming graduate students and outgoing undergraduate students in our department. These are just some of the highlights; he has done so much more!

Thanks for all your efforts Dustin. Very often these sorts of things go unnoticed. I’m glad that was not the case here.

-Ryan

Power side-channel attacks are a means to extract privileged information, such as secret cryptographic keys, from computational hardware by measuring the subtle variations in voltage drop during the times when the secret data is being computed upon. This is a remarkably simple and effective way to recover secret information using low-cost test equipment.

Our recent research with computer engineers at UW and architects at UCSB brought together hardware design, computer architecture, and statistics to identify and programmatically “blink” the processor when the most information leakage occurs. While blinking, the processor is disconnected from the main power supply and running from an internal capacitor, so that attackers cannot obtain information from measurements of voltage drop during those times. We also explore the trade-offs between area overhead and security, introduce a technique for determining if obvious information leakage exists at processor design time, and a statistical approach to localize this leakage.

These ideas are detailed in our paper, “Hiding Intermittent Information Leakage with Architectural Support for Blinking,” which is being presented at the International Symposium on Computer Architecture (ISCA) in June 2018. Have a look at our two-minute lightning talk to get a better idea of how employ hardware blinking to make it more secure against to side channel leakage.

“The best book is a finished book” – Anyone that has written a book

Stephen Neuendorffer (Xilinx), Janarbek Matai (Cognex), and I recently “published” the open-source book “Parallel Programming for FPGAs“, which describes how to effectively use high-level synthesis (HLS) tools to program field programmable gate arrays (FPGAs). High-level synthesis is the process of taking an application written in procedural code (e.g., written as C code) and translating it into a hardware design (e.g., like one written in Verilog). HLS tools are seeing a growing usage in the industry as commercial offerings like Xilinx Vivado HLS become more sophisticated. Yet, these tools require the user to understand parallel programming concepts like data partitioning, pipelining, and task level parallelism. These are non-trivial ideas that often are not covered in a programming course. The book aims to clearly explain these concepts while walking through the design and optimization of different applications.

Don’t understand this? Read our book!

The book is open-source with the hope that it will be a living book. We can quickly and easily fix typos, grammar, and poorly written sections. And we can add new materials. You can probably expect at least minor updates during the times when I’m using the book to teach 237C (typically Fall Quarter). We are very open to receiving contributions of new materials, e.g., additions to existing chapters, new chapters, projects, labs, slides, etc.. We would be happy to provide an appropriate level of attribution (e.g., as a chapter author?). Get in touch with me if you are interested in contributing.

Like anything worth doing, this took a lot longer than anticipated (like 5 years longer!), but I am happy to say that we finally got this manuscript into good enough shape to call it version 1.0. Thanks to Steve for making the final push earlier this year. Janarbek was instrumental in providing a lot of the code examples (certainly for all the chapters that I wrote). Much of this came from his PhD thesis and work as a TA for 237C. And a very special thanks to Xilinx for their funding and immense patience on this. They provided no strings attached funding to my lab to allow my PhD students to work on various aspects of this project. I was also able to leverage incredible support through the Wireless Embedded Systems Masters Program (to fund TAs to work specifically on developing the labs and other teaching materials). I know that everyone would have liked this a lot sooner, but I hope that you will agree that this is better late than never?

We have an associated set of projects that we developed alongside this book over the course of many years in my 237C classes. Cleaning up and releasing these projects will likely be the next major revision to the book. I hope to release them broadly this Fall (no promises especially given my track record on getting this book out in a timely manner!). In the meantime, feel free to get in touch with me if you want to have a look at them.

-Ryan

Related Press: Hackaday

National Geographic announced the Chasing Genius Challenge Finalists which includes undergraduate researcher Nikko Dutra Bouck. Nikko is developing a system that will incentive trash cleanup. It uses low-cost drones to survey an area for trash. Then he plans to develop a Uber/Lyft-like app to pay local people to pick up the trash and deliver it to a landfill. Have a look at his short video for more information and give him a vote while you are there.

The picture shows a large-scale aerial image collected last summer of a mangrove forest in Bahia Magdelena, Mexico. We create this image by stitching together a bunch of pictures that we take from a low-cost drone. It gives us cm-scale resolution which is orders of magnitude better than satellite resolution (like you see on Google Earth). This allows us to zoom in and get fine-grained detail and easily pick out any trash. Even better, we are now working on using automated machine learning algorithms to automatically detect the trash.

Nikko has been working with our research group for more than a year through the Engineers for Exploration program which aims to develop technologies (like this) to aid in conservation, exploration, and cultural heritage. He was awarded an NSF REU scholarship last summer, he is a UCSD FISP awardee, and he leads our collaboration with Octavio Aburto’s group on the mangrove monitoring. He is an amazing person with big goals related to conservation.

Vote now and often and help him take another step towards using the latest technologies to clean up our oceans!