The SmartFin is a surfboard surfin embedded with a number of sensors that allow it to be opportunistically used to gather oceanographic data. The idea is to “crowdsource” the data from surfers all over the globe. This allows us to create fine-grained spatial and temporal sampling strategies to provide data that will ultimately help us better understand complex near-shore environment.

UCSD CSE undergraduate and Engineers for Exploration leader Jasmine Simmons is leading a team in our Engineers for Exploration program working to make the SmartFin even smarter. She has been working closely with oceanographer Phil Bresnahan to create the next version of the SmartFin. One of the major goals is to add the ability to use the SmartFin as a wave sensor. The goal to extract information about the ocean waves (frequency, amplitude, …) from the data gathered from the SmartFin inertial measurement unit (IMU). This is a challenging problem since the IMU data is noisy and the surfer may not always be in a position to collect good data about ocean waves. They are working on developing digital signal processing algorithms to extract the wave data from the sensors on the SmartFin.

The Science Mathematics and Research for Transformation (SMART) program is a US Department of Defense (DoD) scholarship aimed at training top talent in science, technology, engineering and mathematics. SMART fellows are paired with a DoD institution where they spend the summers working on research and then transition into those labs after graduation.

As part of the scholarship, Peter will continue his research with the Naval Information Warfare Center (NIWC) Pacific. Peter’s research looks at how to better use autonomous vehicles (drones and underwater vehicles) to create large scale 3D models. He was been doing research with NIWC Pacific — a large San Diego Navy research facility — for the past couple of years. SMART will allow him to continue this collaboration both during his PhD and after.

Peter is not the first SMART student in our lab. Dr. Chris Barngrover was given a SMART scholarship to fund his PhD thesis on developing novel technologies for finding mines in sonar images. Chris also worked with NIWC Pacific (then SPAWAR).

Higher-Order Functions are a common and convenient way to encapsulate design patterns in software development. However, they are not readily available in hardware design tools. This is because they rely on memory allocators to implement dynamic lists, polymorphism, and looping. These concepts are not very amenable to hardware synthesis.

Dustin presented a solution to this problem in the paper “Higher-Order Functions for C++ Synthesis” at CODES+ISSS as part of Embedded Systems Week. The project develops a library of higher-order functions for C++ High-Level Synthesis tools. We open-sourced these libraries and we hope that you use them. Check that out on github: github.com/drichmond/hops (hops stands for Higher-Order PatternS and also an ode to one of our favorite beverages.). ESWeek was in Torino, Italy so Dustin also found some free time to visit Mont Blanc (pictured).

Once again we had a good showing at 28th International Conference on Field Programmable Logic and Applications (FPL 2018). FPL is the premier European venue for publishing research results in the field of FPGAs and reconfigurable systems. This year, the conference was held in Dublin Ireland. Michael Barrow made the trip to present our two papers.

The first paper was “Everyone’s a Critic: A Tool for Exploring RISC-V Projects”, which describes a tool that provides a way to compare and evaluate the different RISC V architectures with a streamlined suite of tutorials, drivers, and deployment packages on the Pynq development board. The tool is open source at on the github repo: https://github.com/drichmond/RISC-V-On-PYNQ . This project was lead by Dr. Dustin Richmond with contributions by Michael Barrow.

The second paper was “A FPGA Accelerator for Real-Time 3D Non-Rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation”. This project developed a novel reconfigurable system that performs real-time 3D registration — a fundamental computer vision problem with applications in augmented reality, 3D modeling, and computer vision. The architecture was developed with Stephen Burns from Intel (and the result of the time project lead Michael Barrow internship there). Our system is more energy efficient and higher performing than comparable software or hardware approaches with a minimal reduction in registration accuracy.

Hardware design is not easy. It typically involves writing code in low-level languages like Verilog where you must specify how every operation works at every cycle. Modern processors perform billions of operations per second making this is a very difficult task! Yet, hardware design has become increasingly important and more pervasive with the advent of custom accelerators which are used in phones, cars, and in the cloud. We need more hardware designers, but unfortunately, hardware design is hard.

Dr. Dustin Richmond recently defended his PhD thesis that tackled this problem — increasing the accessibility of hardware development to non-hardware engineers through the use of common parallel patterns. As part of this, Dustin developed RIFFA (abstracting communication patterns) [1] and created a framework for synthesizing higher-order functions to hardware (abstracting computational patterns) [2].

As with most PhD students in our research group, Dustin had many side projects to distract him during his PhD career. Dustin played a key role in developing our 3D imaging system for creating 3D scans of Maya archaeological sites. This involved expeditions to Guatemala to scan ancient Maya structures, a run-in with a large black snake, and a publication in “Advances in Archaeological Practice” [3]. Dustin also built the hardware for a high framerate 3D imager in one of our first projects with Cognex [4]. This ultimately helped inform Cognex on how to build this sensor which is now a product. Dustin spent two separate internships at Altera (now Intel) and Xilinx. I’m not entirely sure how he fit all of that into one PhD, but certainly, it is impressive.

While PhD defense is mostly focused on research, it should be noted that Dustin has an equally impressive record with university service and teaching. His efforts to our community have been documented in other posts (CSE award and UCSD Graduate Student Association Awards). As a TA, he took on a major revision of our hardware curriculum in the Wireless Embedded Systems Masters Program. He introduced the Xilinx Pynq platform with a series of labs, lectures, and assignments. For the final project, he organized a hackathon where each group was able to make an impressive project in less than two weeks. We will continue to use this curriculum moving forward in that and other classes.

Dustin will continue on the academic route moving back to the Pacific Northwest to be a postdoctoral scholar with Michael Taylor and Luis Ceze. Look for him on the academic job market in 1-2 years.

-Ryan

Dr. Alric Althoff successfully defended his PhD thesis “Statistical Metrics of Hardware Security”, which helps answer a fundamental question: How secure is your hardware? This is a difficult task — defining what it means to be secure is something that the computer security field has grappled with for decades.

There has been a bevy of high profile attacks on hardware most famously Spectre and Meltdown. It is no longer a question of is your hardware secure (that is easy to answer — it is not), but rather how do we know whether a mitigation technique or run-time vulnerability detection mechanism is effective? Alric developed a set of metrics aimed at answering this question. These metrics enable you to rank when your design is most vulnerable to a power side channel attack, answer questions about the randomness of your random number generator, and determine how hardware optimizations and design decisions affect the leakage of secure information.

While we are on the topic of metrics and definitions, I do not yet know how to define “data science” (nor do I think that term will be properly defined for some time), but I do know that Alric is an exemplar of a data scientist. He is able to quickly understand a problem and come up with elegant solutions to those problems. Thus, it is not surprising that Alric has a been a tour de force for our research group playing prominent roles in almost all of our projects. One of my mantras for the past several years has been “You really should talk to Alric about this.”. His thesis is impressive, and yet this is only a small subset of his research during his PhD tenure.

Luckily (for us) Alric is not moving far; he took a position at Leidos just across the street from campus. Hopefully, we can continue to leverage his expertise going forward.

Congrats Dr. Althoff, best of luck in the future, and don’t be a stranger!

-Ryan

Dr. Perry Naughton successfully defended his PhD titled “Self-localization of a mobile swarm of underwater vehicles using ambient acoustic noise”. His thesis developed a series of techniques that enabled swarms of underwater vehicles to determine their positions by only listening to the ambient ocean noise.

Underwater localization is an important yet difficult problem since water severely attenuates the GPS signals — it only propagates very short distances (tens of centimeters) and thus we typically rely on active acoustic solutions to localize underwater vehicles. These require extensive infrastructure (e.g., deploying buoys) or are costly (e.g., a Doppler velocity logger costs thousands of USD). Using ambient noise is attractive since it only requires the vehicles to have a microphone which simple and cheap (only tens of USD). Perry’s research showed that it is possible to estimate the geometry of a swarm of mobile, underwater vehicles with ambient acoustic noise.

Doing this work required a large network of collaborators. Perry worked closely with the Jaffe Lab to use their Autonomous Underwater Explorers to validate his ideas. And he spent a year in Grenoble working closely with Philippe Roux on some of the more theoretical aspects of his research. Additionally, he worked with a number of other scientists as part of Engineers for Exploration and CISA3. His “side projects” involved imaging shipwrecks, scanning archaeological sites, and creating large-scale 3D models of coral reefs.

Perry received a large number of fellowships and awards over the years including the NSF Graduate Research Fellowship, NSF Integrative Training and Research Award, NSF Graduate Opportunities World Wide, Chateaubriand STEM Scholarship (French Embassy), Friends of the International Center Scholarship, ARCS Foundation, and the Henry Booker Prize for Ethical Engineering.

Congrats Dr. Naughton! You’ve had an impressive UCSD career over the past decade (Perry was an undergrad here before doing his PhD). You will be missed, but we look forward to seeing the great things that you will do.

The Department of Computer Science and Engineering gave Dustin Richmond one of its annual awards for “Excellence in Service/Leadership”. Dustin has been a key leader in departmental activities since the day that he arrived N years ago. He has been an active community leader in our department, interacting with staff, students, and faculty to improve our community by organizing and motivating others to do the same. For example, he was the student chair of the department Graduate Community Council. As part of this, he proposed, designed, and oversaw the remodel of Chez Bob. These changes have transformed the lounge into a common meeting area. For several years he also managed the Graduate Student Association budget, allocating money to ideas and projects that improve the quality of life, evaluating and funding ideas that clearly benefit a broad swath of the department, and helping students make their ideas a reality. Dustin also organized an NSF Graduate Research Fellowship Panel, where current applicants can ask questions, and receive feedback about their essay writing service. He has mentored and encouraged other students in the community and recruited faculty with past NSF application experience to participate. This provides a valuable benefit to incoming graduate students and outgoing undergraduate students in our department. These are just some of the highlights; he has done so much more!

Thanks for all your efforts Dustin. Very often these sorts of things go unnoticed. I’m glad that was not the case here.

-Ryan

Power side-channel attacks are a means to extract privileged information, such as secret cryptographic keys, from computational hardware by measuring the subtle variations in voltage drop during the times when the secret data is being computed upon. This is a remarkably simple and effective way to recover secret information using low-cost test equipment.

Our recent research with computer engineers at UW and architects at UCSB brought together hardware design, computer architecture, and statistics to identify and programmatically “blink” the processor when the most information leakage occurs. While blinking, the processor is disconnected from the main power supply and running from an internal capacitor, so that attackers cannot obtain information from measurements of voltage drop during those times. We also explore the trade-offs between area overhead and security, introduce a technique for determining if obvious information leakage exists at processor design time, and a statistical approach to localize this leakage.

These ideas are detailed in our paper, “Hiding Intermittent Information Leakage with Architectural Support for Blinking,” which is being presented at the International Symposium on Computer Architecture (ISCA) in June 2018. Have a look at our two-minute lightning talk to get a better idea of how employ hardware blinking to make it more secure against to side channel leakage.

 

 

“The best book is a finished book” – Anyone that has written a book

Stephen Neuendorffer (Xilinx), Janarbek Matai (Cognex), and I recently “published” the open-source book “Parallel Programming for FPGAs“, which describes how to effectively use high-level synthesis (HLS) tools to program field programmable gate arrays (FPGAs). High-level synthesis is the process of taking an application written in procedural code (e.g., written as C code) and translating it into a hardware design (e.g., like one written in Verilog). HLS tools are seeing a growing usage in the industry as commercial offerings like Xilinx Vivado HLS become more sophisticated. Yet, these tools require the user to understand parallel programming concepts like data partitioning, pipelining, and task level parallelism. These are non-trivial ideas that often are not covered in a programming course. The book aims to clearly explain these concepts while walking through the design and optimization of different applications.

The book is open-source with the hope that it will be a living book. We can quickly and easily fix typos, grammar, and poorly written sections. And we can add new materials. You can probably expect at least minor updates during the times when I’m using the book to teach 237C (typically Fall Quarter). We are very open to receiving contributions of new materials, e.g., additions to existing chapters, new chapters, projects, labs, slides, etc.. We would be happy to provide an appropriate level of attribution (e.g., as a chapter author?). Get in touch with me if you are interested in contributing.

Like anything worth doing, this took a lot longer than anticipated (like 5 years longer!), but I am happy to say that we finally got this manuscript into good enough shape to call it version 1.0. Thanks to Steve for making the final push earlier this year. Janarbek was instrumental in providing a lot of the code examples (certainly for all the chapters that I wrote). Much of this came from his PhD thesis and work as a TA for 237C. And a very special thanks to Xilinx for their funding and immense patience on this. They provided no strings attached funding to my lab to allow my PhD students to work on various aspects of this project. I was also able to leverage incredible support through the Wireless Embedded Systems Masters Program (to fund TAs to work specifically on developing the labs and other teaching materials). I know that everyone would have liked this a lot sooner, but I hope that you will agree that this is better late than never?

We have an associated set of projects that we developed alongside this book over the course of many years in my 237C classes. Cleaning up and releasing these projects will likely be the next major revision to the book. I hope to release them broadly this Fall (no promises especially given my track record on getting this book out in a timely manner!). In the meantime, feel free to get in touch with me if you want to have a look at them.

-Ryan

Related Press: Hackaday