The Office of Naval Research held a workshop aimed to identify key research areas for offensive of defensive hardware security research, metrics to measure high assurance, and approaches to mitigate threats. And ideally these are all deployable in the short term without modifications to the hardware. This is a tall task for sure. Ryan presented our group’s research on hardware security design tools including security testing and verification, metrics based upon information theoretic measures, and the need to employ application driven research. The workshop was hosted by Simha Sethumadhavan at Columbia University. The requisite foot picture of Columbia’s campus to prove that I was there.

The PROOFS workshop is held annually alongside CHES and CRYPTO with the goal of “promoting methodologies that increase the confidence level in the security of embedded systems, especially those which contain cryptographic algorithms”. Ryan was invited to give a keynote talk on hardware security design tools. This year the workshop was held at UC Santa Barbara, which gave Ryan the opportunity to visit his old stomping grounds (he was a professor there from 2002-2007). If you are interested, you can use the Internet “Wayback Machine” and see our old research group’s website. The painting is of UCSB Campus Point. It hangs on the wall in Ryan’s house.

Hardware Trojans are tiny pieces of circuitry that hide amongst millions, or even billions of transistors. They lay dormant until some hard to detect trigger springs them into action. Then the start their malicious behaviors like draining power or leaking secret information. The are by design difficult to detect, but our recent research shows that information flow tracking is a useful way to find and eliminate them. The research was a cover feature for the August issue of IEEE Computer. The paper’s authors are Kastner Research Group (KRG) Postdoc Wei Hu, Computer Science and Technology Ph.D. candidate Baolei Mao of Northwestern Polytechnical University (and former KRG visiting graduate student), Tortuga Logic CEO Jason Oberg, and CSE Professor Ryan Kastner. Three of the four authors (Baolei is missing) are shown a couple years ago taking in the sites at Xi’an.

Links: IEEE Computer Article, UCSD Press Release, UCSD CSE news article, QI Press Release, JSOE Press Release, Cyberwire, eWeek

Michael Barrow was one of 14 students awarded the new SIGHPC/Intel fellowship. ACM’s Special Interest Group on High Performance Computing (SIGHPC), in collaboration with Intel, established the fellowship to increase the diversity of students pursuing graduate degrees in data science and computational science, including women as well as students from racial/ethnic backgrounds that have not traditionally participated in the computing field. The fellowship starts in August, but Mike will be recognized during the high performance computing community’s flagship Super Computer (SC) conference this November.  Mike’s research focuses on developing high performance vision systems to aid surgeons during operations.

Links:
InsideHPC
HPCWire

Perry will be spending next year at ISTerre in Grenoble, France working on part of his thesis under Dr. Philippe Roux. Perry received support through the NSF Graduate Research Opportunities Worldwide (GROW) program, the Chateaubriand STEM Fellowship, and the Friends of the International Center Scholarship to encourage this international collaboration. Dr. Roux performed many of the early experiments that inspired Perry’s thesis – using ambient acoustic noise in the ocean for relative localization of moving receivers. Perry is excited to expand many of these theories under Dr. Roux’s supervision and is busy collecting data with Autonomous Underwater Explorers this summer to provide new datasets to study.

Ryan gave an invited talk at the UCSD Design Lab‘s Design@Large Seminar. The talk went through the history of three of our projects – building technology for behavioral animal monitoring, documenting Maya culture, and coral reef visualization. We have certainly gone through a lot of different prototypes, and made a number of good (and bad) design decisions in developing the technology for these projects. The entire talk was recorded and viewable on the Design Lab Youtube channel.

The National Science Foundation recently renewed our Engineers for Exploration summer research program. The funding allows us to bring in 10+ undergraduates from around the country for a 10 week summer experience focusing on building technology to aid in ecology, biology, oceanography, and archaeology. The students partake in cyber-physical systems research motivated by real world challenges in exploration and scientific discovery. The program for this summer starts June 20.

Related Links: NSF Award Announcement, Engineers for Exploration Website

The first Southern California Robotics Symposium was recently held at the Qualcomm Institute at UCSD. The event brought over 200 people from industry, academia and private research institutes to present and discuss cutting-edge research. Our group was well represented with demonstrations of our Engineers for Exploration projects, our underwater imaging prototypes, and data visualizations from our various expeditions.

CALIT2 News Release, JSOE News Release

Spatiotemporal analytics — the time and place that you tweet, post, and login — is getting increased interest in data science research. Geohash is a novel and efficient way to provide a location in lieu providing a latitude and longitude. As described in the recently published paper, “Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware””, Geohash operations are ripe for implementation on an FPGA due to its bit-level encoding system. This paper was published at the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). Dajung worked on this research project last summer during her internship at IBM Research. Dajung presented the work at FCCM. Congrats to Dajung and her co-authors Roger Moussalli, Sameh Asaad, and Mudhakar Srivatsa.

Our paper, Tinker: Generating Custom Memory Architectures for Altera’s OpenCL Compiler was accepted at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)! Deploying High Level Synthesis hardware design tools and integrating them with existing interfaces is a major challenge. In this paper we introduce Tinker, an open-source Board Support Package generator for Altera’s OpenCL Compiler. Board Support Packages define memory, communication, and other ports for easy integration with high level synthesis cores. Tinker abstracts the low-level hardware details of hardware development when creating board support packages and greatly increases the flexibility of OpenCL development. Tinker allows users to generate custom memory architectures, providing a new method for kernel optimization that was not available before. Congratulations to the authors: Dustin, Matt, Jeremy, Kevin, and Ryan!

You can download Tinker from the Git Repository: Tinker Git Repo