First Technique for Detecting Hardware Timing Channels

test_flowThe article “Leveraging Gate Level Properties to Identify Hardware Timing Channels” was accepted to the IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD). Jason was the lead author along with co-authors Sarah Meiklejohn (UCSD), Timothy Sherwood (UCSB), and Ryan. This paper formalizes how Gate Level Information Flow Tracking can be used to detect timing channels: a form of information leak where secret information can affect run time.