The latest and greatest version of RIFFA has been released. RIFFA is a framework that enables designers to easily communicate between FPGAs and CPUs over a PCIe bus. This work was born out of immense frustration of building complete hardware accelerated systems. Previous to RIFFA, there was no easy to use way to create an CPU/FPGA hybrid system that could take advantage of the power computing abilities of FPGAs while at the same time utilize the flexibility and interoperability of software running on CPUs. RIFFA changed that and is currently being used by designers around the world.

The latest updates to RIFFA include a complete redesign of the FPGA interfacing. This enables user to easily extend it to work with other FPGAs and development boards. The primary developers of this project are Kastner Group PhD alumni Matt Jacobsen and current PhD student Dustin Richmond. The work has been funded by Altera, Intel, and Xilinx. It was the recipient of the FPL Community Award in 2013.

Links:
RIFFA webpage
Xilinx Xcell Daily Blog
UCSD Qualcomm Institute Press Article
UCSD Computer Science and Engineering Press Article
FPL Community Award

The NCWIT Collegiate Award Honorable Mention – given by the National Center for Women & Information Technology and HP – was presented to Antonella Wilby. Antonella has been a member of our Engineers for Exploration program working on a project related to developing underwater sensing technology to document the shipwrecks and other underwater archaeological artifacts. Each honorable mention received a $500 cash gift, an HP backpack and gift, and recognition at an awards ceremony at the NCWIT 2015 Summit in Hilton Head, SC. Congrats to Antonella!

NCWIT Announcement

Side channels are a commonly exploited to derive secret information from hardware. These leak information through unintended sources, e.g., the amount of time to perform an encryption. They have been shown to be a powerful attack to extract cryptographic keys and other confidential information. There are many defenses against these timing side channel attacks. Most of them perform some sort of randomization in an attempt to mask the computation time. Yet, it has been difficult to quantify the benefit of these defenses.

Our recent research provides a metric to allow designers to determine how resilient their design is in the face of a side channel attack. While there are many metrics for hardware designers, these have focused on performance, power, and area. We developed information theoretic approaches and showed that they can be used to quantify timing-based information leakage. This is detailed in our recently accepted paper, “Quantifying Timing-Based Information Flow in Cryptographic Hardware” at the International Conference on Computer Aided Design. Vinnie will present the paper in Austin, TX in November. Congrats to all the authors: Baolei Mao, Vinnie Wei Hu, Alric Althoff, Janarbek Matai, Jason Oberg, Dejun Mu, Tim Sherwood, and Ryan Kastner.