We received an Amazon Web Services (AWS) Grant for our research on how to use machine learning to aid design space exploration of the high level synthesis (HLS) tools. Compiling a design to an FPGA is extremely time consuming (it can take days of compute time for compilation). Moreover, our research requires tens of thousands of these synthesis runs for the purpose of training better machine learning strategies. Collecting this amount of data could take several years even on a high-end workstation. For this reason, it was almost impossible to collect enough data for our research on the computer equipment in our lab. Now, with this grant ($15,300 of AWS credits), we are able to collect this data by running the process on AWS in parallel. The AWS parallel computing power will significantly speedup this process. Thanks to the AWS academic program, we now have the opportunity to further understand the nature of the hardware design spaces and build better machine learning strategies to aid application designers in the future. For those looking for more details, our initial research efforts in this space has been accepted at DATE 2016 in the article “Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs”.