Overview
Many of the fundamental digital signal processing transformations are modeled as linear systems, including Finite Impulse Response (FIR) filters, Discrete Cosine Transform (DCT) and H.264 video compression. These transforms are often major determinants of the overall system performance; hence their optimization is paramount to achieve lower power consumption, higher throughput, and faster response time.

Benchmarks
We receive many request for the benchmarks that we used in our papers. The following have appeared in many of them. They can be normalized by dividing by 16384 (2^14).

8-point DCT
8-point DFT
8-point DHT
8-point DST
H.264
8-point Inverse DCT

Relevant Publications

Ryan Kastner, Farzan Fallah, and Anup Hosangadi, “Arithmetic Optimization Techniques for Hardware and Software Design“, Cambridge University Press, May 2010, ISBN-13: 9780521880992 (order)

Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Algebraic Methods for Optimizing Constant Multiplications in Linear Systems”, Springer Journal of VLSI Signal Processing, vol. 49, issue 1, pp. 31-50, October 2007 (pdf)

Shahnam Mirzaei, Anup Hosangadi and Ryan Kastner, “Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs“, International Journal of Reconfigurable Computing, Volume 2010, Article ID 697625, January 2010 (pdf)

Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis“, International Conference on Application-specific Systems, Architectures and Processors, September 2004: Acceptance Rate: 30/56 = 53.6% (pdf, slides)

Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Reducing Hardware Complexity of Linear DSP Systems by Iteratively Eliminating Two Term Common Subexpressions“, Asia South Pacific Design Automation Conference (ASP-DAC), January 2005 – Full Paper Acceptance Rate: 14.3% (pdf, slides)

Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Simultaneous Optimization of Delay and Number of Operations in Multiplierless Implementation of Linear Systems”, International Workshop on Logic and Synthesis (IWLS), June 2005 (pdf) – poster presentation

Shahnam Mirzaei, Anup Hosangadi, and Ryan Kastner, “High Speed FIR Filter Implementation Using Add and Shift Method”, International Symposium on Field Programmable Gate Arrays (FPGA), February 2006 – poster presentation

Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Optimizing High Speed Arithmetic Circuits Using Three Term Extraction”, Design, Automation and Test in Europe Conference (DATE), March 2006 – Acceptance Rate: 267/834 = 32% (pdf, slides)

Shahnam Mirzaei, Anup Hosangadi and Ryan Kastner, “FPGA Implementation of High Speed FIR Filter Using Add and Shift Method”, International Conference on Computer Design (ICCD), October 2006 – Acceptance Rate: 31% (pdf, slides)

Arash Arfaee, Ali Irturk, Farzan Fallah and Ryan Kastner, “Xquasher: A Tool for Efficient Computation of Multiple Linear Expressions“, Design Automation Conference (DAC), July 2009 – Acceptance Rate: 21% (pdf)