CSE 237C

Instructor: Prof. Ryan Kastner (kastner@ucsd)
Time: Tuesday-Thursday, 2-3:20pm
Location: Warren Lecture Hall (WLH) 2209
Office Hours: After class or by appointment

Class Description: This class focuses on creating embedded system prototypes using a programmable system-on-chip. The class is graded primarily based on the performance in projects that are spread across the class (one approximately every two weeks). The projects require the student to implement a digital signal processing (DSP) core and integrate it into a prototype wireless RF system. Students will learn how to use modern high-level synthesis tools to create different DSP architectures.

Required Knowledge: This class is part of the 237 “Embedded Systems” series. This class stands on its own and does not require knowledge from any of the previous 237 classes. Having some understanding of basic digital signal processing (sampling, filtering, transforms), and even better wireless systems, is useful but not required. Equally helpful is having taken classes in computer architecture (and in particular understanding pipelining, memory hierarchy, and digital design). Again, it will be useful but not required as the class is taught in a way that is self-contained. Do note that most students have a good background in at least one of these areas (DSP or computer architecture); if you do not know either, then you will have to work harder.

Recommended Preparation for Those Without Required Knowledge: For those who do not know DSP, there are countless resources for this. You would be wise to understand finite impulse response (FIR) filters, discrete Fourier transform, and fast Fourier transforms. These form some of the core computations for the projects. Each of these topics will be described in class, but you would be wise to have at least a decent understanding of how these work. The same is true for computer architecture; there are countless resources for this. You generally want to understand the components of a data path (control flow, data flow) and the tradeoffs in memory design (number of ports, throughput, hierarchy, etc.). We will primarily be using the Xilinx Vivado HLS design tool. There are a number of tutorials on this tool at the Xilinx website. If you want to start using the tool early, contact the instructor.


  • Projects 1-5: 12% each, 60% total
  • Final Project 30%
  • Class Participation – 10%
    • Attendance
    • Questions in class

Class Materials:


Note: These projects are not recent (over two years old). Use the projects posted on Piazza.

Class Calendar: