We are providing the filter benchmarks from our paper “Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs” (if you use these benchmarks, please cite this paper). This will hopefully allow fair comparison between our work and future techniques.
This include a zip file of the coefficients for each of the filters as well as the optimized verilog implementations that we reported in the paper.
There are two sets of files to download. *.coe files represent the coefficients of the FIR filters and *.v files represent the Verilog file.
ex1EP16_6: 6 tap FIR filter
ex4EP16_10: 10 tap FIR filter
ex2EP16_13: 13 tap FIR filter
ex1BT16_20: 20 tap FIR filter
ex1PM16_28: 28 tap FIR filter
ex1LS16_41: 41 tap FIR filter
ex3PM16_61: 61 tap FIR filter
ex2BT16_71: 71 tap FIR filter
ex2PM16_119: 119 tap FIR filter
ex4PM16_152: 152 tap FIR filter