We received an Amazon Web Services (AWS) Grant for our research on how to use machine learning to aid design space exploration of the high level synthesis (HLS) tools. Compiling a design to an FPGA is extremely time consuming (it can take days of compute time for compilation). Moreover, our research requires tens of thousands of these synthesis runs for the purpose of training better machine learning strategies. Collecting this amount of data could take several years even on a high-end workstation. For this reason, it was almost impossible to collect enough data for our research on the computer equipment in our lab. Now, with this grant ($15,300 of AWS credits), we are able to collect this data by running the process on AWS in parallel. The AWS parallel computing power will significantly speedup this process. Thanks to the AWS academic program, we now have the opportunity to further understand the nature of the hardware design spaces and build better machine learning strategies to aid application designers in the future. For those looking for more details, our initial research efforts in this space has been accepted at DATE 2016 in the article “Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs”.
This winter quarter, we welcome a “new” PhD student to our group. But Antonella is fair from a stranger; she has been working with the Engineers for Exploration program for several years now as an undergraduate. Antonella’s work has mostly focused on underwater monitoring. She worked on a variety of different remote sensing projects. Her most recent efforts on focused on saving the vaquita — the most endangered marine mammal in the world. As part of this work, she was named a National Geographic Young Explorer. Her recent post on National Geographic Ocean Views blog provides more details on her efforts. The picture to shows her testing an early version of the SphereCam which is being used to capture photographs of the vaquita. In addition to her National Geographic Award, she received a National Science Foundation Graduate Fellow Honorable Mention in 2015, and was the second UCSD CSE student to be UCSD Sloan Scholar (the first is Kastner Research Group member Jeremy Blackstone). Welcome to the ranks of the graduate students Antonella!
Our friends and collaborators at USC created a short video on the recent field season at the Maya site El Zotz in Guatemala. We spent about a week there developing 3D models of the various artifacts and excavations. See if you can find the Kastner Research Group members in the video.
Our paper “Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis” was accepted as a full paper at the International Symposium on Field-Programmable Gate Arrays (ISFPGA) to be held in Monterey, CA in February 2016. Our Resolve framework allows designers to quickly create generate architectures to meet the requirements of the performance at hand. In particular, Resolve provides ten highly optimized basic sorting architectures; it easily composes basic architectures to generate hybrid sorting architectures; and it enables non-hardware experts to quickly design efficient hardware designs, and easily develop customized heterogeneous FPGA/CPU systems.
This was the “final” paper from Dr. Janarbek Matai’s PhD work. He provided this inspirational quote and sage piece of advice to the other members of the Kastner Research Group: “In case if you are … wondering how it feels like writing a paper after graduation, I will tell you. The function of pain is not logarithmic anymore, it is exponential. … Publish before your graduation.” Wise words indeed. Congrats to Janarbek for not having to feel the logarithmic or exponential pain anymore. And to the other authors (Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, and Ryan Kastner) most of which have a lot of pain to look forward to in the future.
The Kastner Research Group is getting ready for a European Vacation this coming March. We have three long papers accepted at Design Automation and Test in Europe (DATE) which will be held March 14-18, 2016 in Dresden, Germany. DATE is the premier European conference for electronic system design and test. The three papers are “Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs“, “Composable, Parameterizable Templates for High Level Synthesis“, and “Quantifying Hardware Security Using Joint Information Flow Analysis“. The first paper, authored by Pingfan Meng, Alric Althoff, Quentin Gautier, and Ryan Kastner, builds a machine learning framework to determine Pareto optimal designs from OpenCL to FPGAs, with a limited number of synthesis runs (which costs hours or days). The second paper, authored by Janarbek Matai, Dajung Lee, Alric Althoff, and Ryan Kastner, develops a framework for composing high-level synthesis applications from templates. The final paper was invited for a special session on system security. It focuses on a creating a novel hardware security design flow using quantitative metrics. It was authored by Ryan Kastner, Wei Hu, and Alric Althoff. Congrats to all of the authors!
A tradition unlike any other — the Kastner Research Group retreat. Most of the members of the group headed for a few days of adventure, research presentations, and high elevation mountain air last week. The fourth annual installment included the group hike up and around the Crystal Crag near Mammoth Lakes. The five mile hike, with over 1000 feet of elevation gain, was enjoyed by some more than others. But everyone made it and has some stories to tell. The picture shows the group (at least those that survived) with the Crystal Crag in the background. Next year we will try something a little less difficult, e.g., hiking up Mount Everest.
We are pleased to welcome Jeremy Blackstone as the newest PhD student in the Kastner Research Group. However, Jeremy is no stranger; he has worked with us for two summers. In Summer 2013, he worked as a member of the Engineers for Exploration program. Last summer he did research on the RIFFA project. Jeremy graduated magna cum laude in computer science from Howard University, where he also earned his M.S. degree
Jeremy Blackstone is the first graduate student selected to receive a fellowship from the Alfred P. Sloan Foundation Minority Ph.D. Program to do a doctorate in Computer Science and Engineering at the University of California, San Diego. He was also awarded a UC-HBCU fellowship. He graduated magna cum laude in computer science from Howard University, where he also earned his M.S. degree.
We recently received an NSF grant on “Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs”. The project will develop quantitative hardware security metrics that enable designers to precisely evaluate the security of the system. We do this by employing statistical measures on the amount of uncertainty and information flow that is present across different portions of the hardware. These metrics are oblivious to the types of variables under consideration. Thus, we can assess both functional security properties related to confidentiality and integrity as well as covert channels. Our metrics enable the characterization of portions of the system that are potentially vulnerable to attacks. And they determine the effectiveness of mitigation techniques on the overall security of the system. The end result is more secure hardware, which leads to safer and more secure computing devices.
The latest and greatest version of RIFFA has been released. RIFFA is a framework that enables designers to easily communicate between FPGAs and CPUs over a PCIe bus. This work was born out of immense frustration of building complete hardware accelerated systems. Previous to RIFFA, there was no easy to use way to create an CPU/FPGA hybrid system that could take advantage of the power computing abilities of FPGAs while at the same time utilize the flexibility and interoperability of software running on CPUs. RIFFA changed that and is currently being used by designers around the world.
The latest updates to RIFFA include a complete redesign of the FPGA interfacing. This enables user to easily extend it to work with other FPGAs and development boards. The primary developers of this project are Kastner Group PhD alumni Matt Jacobsen and current PhD student Dustin Richmond. The work has been funded by Altera, Intel, and Xilinx. It was the recipient of the FPL Community Award in 2013.
The NCWIT Collegiate Award Honorable Mention – given by the National Center for Women & Information Technology and HP – was presented to Antonella Wilby. Antonella has been a member of our Engineers for Exploration program working on a project related to developing underwater sensing technology to document the shipwrecks and other underwater archaeological artifacts. Each honorable mention received a $500 cash gift, an HP backpack and gift, and recognition at an awards ceremony at the NCWIT 2015 Summit in Hilton Head, SC. Congrats to Antonella!